1. Technical Field
The present invention relates generally to computer systems and in particular to microprocessor architecture. Still more particularly, the present invention provides an improved scannable last-in-first-out (LIFO) register stack.
2. Description of the Related Art
In a computer system, a microprocessor is a single-chip integrated circuit implementation of a general-purpose central processing unit. A microprocessor contains a controller to direct execution of programs, registers to store, control, and data value temporally, and in an arithmetic logic unit to calculate results. A LIFO register stack may be found in microprocessor and other logic designs. In particular, a LIFO register stack is a type of memory element that stores and retrieves information. In this type of memory element, the item stored last is the first item retrieved. LIFO register stacks are commonly found in microprocessors because of their ability to handle recursive operations and the simplicity of addressing these memory elements.
A LIFO register stack may be implemented in a variety of ways known to those of ordinary skill in the art. One implementation is shown in FIG. 1. LIFO register stack 100 in FIG. 1 contains several registers R0-Rm arranged in a stack. Each register contains n bits in n bit locations. The write path is from the direction R0 to Rm while the read path is in the direction Rm toward R0.
The registers are typically arranged in a stack in which each register includes an array of bit locations. m registers and n bit locations are arranged so that the input to a register comes from either the register above or the register below. The read ports in the bit locations in the bottom register are typically unused in this type of configuration. The input to the top register A0 comes either from the data in pod of the stack or the register below. Input to the bottom register, register Am, comes only from the register above it.
Concerning FIG. 2, a logic diagram of circuitry for a bit location in a register in LIFO register stack 100 is depicted. In this depicted example, the circuitry is for bit location j in register i. The circuitry contains a multiplexer 110 and a latch 112. In the depicted example, latch 112 is a master/slave latch. Multiplexer 110 has a write input w and a read input r. Additionally, a hold input is present in multiplexer 110. Multiplexer 110 also includes enable inputs 114 and 116. Enable input 114 allows the signal at write input w to be sent to input d in latch 112 while an enable signal at input 116 allows the signal connected to read input r to be sent to input d.
For bit location j in register i, write input w is connected to bit location j in register i-1 and read input r is connected to bit location j in register i+1. Latch 112 has an output q connected to bit location j of register i-1 and bit location j of register i+1. Master clock signal mck and slave clock signal sck are employed to clock data through latch 112.
Generally, two operations control the function of LIFO stack register 100 in FIG. 1. A write to the stack (also called a "push") adds another item to the top of the stack. Items already in the stack are shifted down so that the item stored in register i moves to register i+1. Any item stored in the register at the bottom of the stack "falls off" the bottom of the stack and is lost in a write operation.
A read of the stack (also called a "pop") removes the item located in the top of the stack. In response to the top item being removed, other items in the stack are shifted upward such that the item stored in register i moves into register i-1. The contents of the register at the bottom of the stack are undefined after a read operation. As a result, if the number of "pops" ever exceeds the number of "pushes" the data taken from the stack will be invalid then. Monitoring logic is typically employed to ensure that such invalid data is ignored.
The sequential nature of access to lower regions of the stack typically takes i+1 writes followed by i+1 reads to exercise and observe the contents of register i. This type of access makes the stack very difficult to test without special provisions. Often employing scan techniques to provide complete test coverage of the stacks is important.
In scanning a stack, selected data is written into every bit location in every register of the stack to "set" the state of the stack. After the contents of a stack has been set by a scan, the LIFO register stack may then be tested. One way to add scan to a LIFO register task is to apply standard scan techniques to the registers in the stack. Such a technique requires adding a scan input to every latch employed in the LIFO register stack and a corresponding scan clock controlling the scan operation of the stack. FIG. 3 depicts a LIFO register stack 130. This register stack is similar to the one depicted in FIG. 1 except that a scan input 132 has been added to the stack and a scan output 134 has been added. In such a scan path, data is scanned from bit location to bit location within each register with the last bit location at an end of one register feeding to the first bit location of the succeeding register as depicted in FIG. 3.
FIG. 4 shows a logic diagram for a bit location in a register in FIG. 2. Multiplexer 140 is configured in the same manner as multiplexer 110 in FIG. 2. Latch 142 is similar to latch 112 except that an additional input sd has been included for scan data and an additional input for scan clock scnck has been added. Output q of latch 142 also is connected to bit location j+1 in register i to allow shifting of data across the register when data is scanned through the LIFO register stack.
As can be seen, the additional input into latch 142 requires extra devices and logic circuits to handle the input during a scan. Other scan techniques presently known may require extra clocking in addition to extra devices and logic circuits. The addition of extra circuits and clocks can degrade the overall performance of the microprocessor or logic design in which the LIFO register stack is implemented. Therefore, having an improved LIFO register stack that is scannable would be advantageous, but does not require additional devices, logic circuits, or clocking to provide a scanning capability.